   1              		.syntax unified
   2              		.cpu cortex-m3
   3              		.fpu softvfp
   4              		.eabi_attribute 20, 1
   5              		.eabi_attribute 21, 1
   6              		.eabi_attribute 23, 3
   7              		.eabi_attribute 24, 1
   8              		.eabi_attribute 25, 1
   9              		.eabi_attribute 26, 1
  10              		.eabi_attribute 30, 4
  11              		.eabi_attribute 34, 1
  12              		.eabi_attribute 18, 4
  13              		.thumb
  14              		.syntax unified
  15              		.file	"ssp1.c"
  16              		.text
  17              	.Ltext0:
  18              		.cfi_sections	.debug_frame
  19              		.section	.text.spi1_SetBitsPerTransfer,"ax",%progbits
  20              		.align	1
  21              		.global	spi1_SetBitsPerTransfer
  22              		.thumb
  23              		.thumb_func
  25              	spi1_SetBitsPerTransfer:
  26              	.LFB1:
  27              		.file 1 "uc_libc_dev/_arch/arm_lpc/spi/ssp1.c"
   1:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // data de ataulização: 2014/07/09
   2:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
   3:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** #include "ssp1.h"
   4:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** #if defined(cortexm3)
   5:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** #include "arm.h"
   6:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** #endif
   7:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
   8:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** #if (SSP1_USE_DEBUG	== pdON)
   9:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** #include"stdio_uc.h"
  10:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** #endif
  11:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
  12:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // TODO: COLOCAR TIMEROUTS NOS WHILES INFINITOS
  13:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //-------------------------------------------------------------------------------------------------
  14:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Descrição: 	Incializa o barramento SSP
  15:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // parametros	mode: Modo da CPU
  16:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //					SSP1_MASTER
  17:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //					SSP1_SLAVE
  18:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //				config:
  19:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //					SSP1_CPHA_[L/H] | SSP1_CPOL_[L/H] | SSP1_BITS_[16:4] | FORMAT_FRAME
  20:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //						FORMAT_FRAME: SSP1_FRF_SPI, SSP1_FRF_SSI ou SSP1_FRF_MW
  21:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //							SSP1_FRF_SPI: Formato frame = SPI
  22:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //							SSP1_FRF_SSI: Formato frame = TI
  23:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //							SSP1_FRF_MW:  Formato frame = Microwire
  24:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //						SSP1_BITS_[16:4]: Determina os bits de transferencia onde x sinaliza de 8 a 16 bits.
  25:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //						SSP1_CPHA_L: Dados capturados na primeira borda do clock
  26:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //						SSP1_CPHA_H: Dados capturados na segunda borda do clock
  27:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //						SSP1_CPOL_L: Clock em baixa entre os frames
  28:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //						SSP1_CPOL_H: Clock em alta entre os frames
  29:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //					SSP1_STANDARD Tem valor 0x7. Ajusta o modo padrão para a SSP, ou seja, transmissão com 8 bit
  30:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Retorna: 	Nada
  31:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //-------------------------------------------------------------------------------------------------
  32:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** void ssp1_Init (u8 mode, u16 config) {
  33:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	u32 i;
  34:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	volatile u32 dummy __attribute__ ((unused)); // Usar atributo para não emitir aviso pelo compila
  35:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	
  36:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	PCONP |= PCSSP1;
  37:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	#if defined (arm7tdmi)
  38:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	SSP1_PINSEL = (SSP1_PINSEL & ~SSP1_PINMASK) | SSP1_PINS; 			// Seleciona o pino externo para a f
  39:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	#endif
  40:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
  41:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	#if defined (cortexm3)
  42:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	#if defined (LPC1788)
  43:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	pinsel_cfg_t pinCFG;
  44:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	pinCFG.addrPort = &SSP1_PINSEL; 	// Endereço da porta SSP1
  45:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	pinCFG.numPin = SSP1_CLK_NUMPIN;	// Número do pino do ARM para o CLK
  46:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	pinCFG.nunFunc = SSP1_NUNFUNC;		// Ajustado a função do pino para SSP
  47:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	pinCFG.openDrain = 0;				// Dreno aberto desligado
  48:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	pinCFG.pinMode = 0;					// Sem resistor de pull
  49:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	pinsel_configPin(&pinCFG);			// Aplica configurações
  50:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	pinCFG.numPin = SSP1_MISO_NUMPIN;	// Número do pino do ARM para o MISO
  51:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	pinsel_configPin(&pinCFG);			// Aplica configurações
  52:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	pinCFG.numPin = SSP1_MOSI_NUMPIN;	// Número do pino do ARM para o MOSI
  53:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	pinsel_configPin(&pinCFG);			// Aplica configurações
  54:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	#else
  55:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 		ssp1_ConfigPort();
  56:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	#endif
  57:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	#endif
  58:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
  59:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	SSP1CR0  = config; // | SSP1_FRF_SPI;
  60:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	spp1_SetMode( mode );
  61:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	SSP1IMSC = 0x0;
  62:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	
  63:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	//  Clock Freq. Identification Mode < 400kHz
  64:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	ssp1_SetClockFreq (400000);
  65:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
  66:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	//  Enable SPI
  67:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	SSP1CR1 |= SSP1_SSE_ON; // Habilita SSP
  68:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
  69:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	#if (SSP1_USE_DEBUG	== pdON)
  70:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	plog("SSP1: INIT"CMD_TERMINATOR);
  71:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	plog("SSP1: SSP0CR0 %u"CMD_TERMINATOR, SSP1CR0);
  72:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	plog("SSP1: SSP0CR1 %u"CMD_TERMINATOR, SSP1CR1);
  73:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	#endif
  74:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
  75:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	for (i = 0; i < 8; i++)
  76:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	dummy = SSP1DR;
  77:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** }
  78:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
  79:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //-------------------------------------------------------------------------------------------------
  80:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Descrição: 	Ajusta o número de bits na transferencia de dados
  81:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // parametros	bits:  SSP1_DSS_x ( x de 4 a 16)
  82:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //				Determina os bits de transferencia onde x sinaliza de 8 a 16 bits. Somenente o lpc2468, lpc21
  83:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Retorna: 	Nada
  84:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //-------------------------------------------------------------------------------------------------
  85:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** void spi1_SetBitsPerTransfer(u16 bits) {
  28              		.loc 1 85 0
  29              		.cfi_startproc
  30              		@ args = 0, pretend = 0, frame = 0
  31              		@ frame_needed = 0, uses_anonymous_args = 0
  32              		@ link register save eliminated.
  33              	.LVL0:
  86:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	SSP1CR0 &=~ SSP1_DSS_MASK;
  34              		.loc 1 86 0
  35 0000 044B     		ldr	r3, .L2
  36 0002 1A68     		ldr	r2, [r3]
  37 0004 22F00F02 		bic	r2, r2, #15
  38 0008 1A60     		str	r2, [r3]
  87:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	SSP1CR0 |= bits;
  39              		.loc 1 87 0
  40 000a 1A68     		ldr	r2, [r3]
  41 000c 1043     		orrs	r0, r0, r2
  42              	.LVL1:
  43 000e 1860     		str	r0, [r3]
  44 0010 7047     		bx	lr
  45              	.L3:
  46 0012 00BF     		.align	2
  47              	.L2:
  48 0014 00000340 		.word	1073938432
  49              		.cfi_endproc
  50              	.LFE1:
  52              		.section	.text.ssp1_SetClockFreq,"ax",%progbits
  53              		.align	1
  54              		.global	ssp1_SetClockFreq
  55              		.thumb
  56              		.thumb_func
  58              	ssp1_SetClockFreq:
  59              	.LFB2:
  88:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
  89:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	#if (SSP1_USE_DEBUG	== pdON)
  90:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	plog("SSP1: SET BITS TRANS"CMD_TERMINATOR);
  91:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	plog("SSP1: SSP0CR0 %u"CMD_TERMINATOR, SSP1CR0);
  92:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	#endif
  93:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** }
  94:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
  95:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //-------------------------------------------------------------------------------------------------
  96:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Descrição: 	Ajusta a frequencia do barramento
  97:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // parametros	frequency: velocidade do barramento e HZ
  98:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //					cortexm3 max 10Mhz, para os demais 400KHz
  99:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Retorna: 	A frequencia ajustada no barramento
 100:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //-------------------------------------------------------------------------------------------------
 101:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** u32 ssp1_SetClockFreq(u32 frequency) {
  60              		.loc 1 101 0
  61              		.cfi_startproc
  62              		@ args = 0, pretend = 0, frame = 0
  63              		@ frame_needed = 0, uses_anonymous_args = 0
  64              		@ link register save eliminated.
  65              	.LVL2:
 102:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	u32 div = PCLK / frequency;
  66              		.loc 1 102 0
  67 0000 094B     		ldr	r3, .L8
  68 0002 B3FBF0F0 		udiv	r0, r3, r0
  69              	.LVL3:
 103:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 104:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	if (div < 8)    	div = 8;
  70              		.loc 1 104 0
  71 0006 0728     		cmp	r0, #7
  72 0008 1A46     		mov	r2, r3
  73 000a 03D9     		bls	.L6
  74 000c FE28     		cmp	r0, #254
  75 000e 28BF     		it	cs
  76 0010 FE20     		movcs	r0, #254
  77              	.LVL4:
  78 0012 00E0     		b	.L5
  79              	.LVL5:
  80              	.L6:
  81 0014 0820     		movs	r0, #8
  82              	.LVL6:
  83              	.L5:
 105:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	//if (div < 1)    	div = 2;
 106:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	else if (div > 254) div = 254;
 107:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 108:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	++div; 
  84              		.loc 1 108 0
  85 0016 431C     		adds	r3, r0, #1
  86              	.LVL7:
 109:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	div &= ~1;
 110:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	SSP1CPSR = div;
  87              		.loc 1 110 0
  88 0018 0449     		ldr	r1, .L8+4
 109:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	div &= ~1;
  89              		.loc 1 109 0
  90 001a 23F00100 		bic	r0, r3, #1
  91              	.LVL8:
  92              		.loc 1 110 0
  93 001e 0860     		str	r0, [r1]
 111:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	
 112:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	#if (SSP1_USE_DEBUG	== pdON)
 113:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	plog("SSP1: PLCK      %u"CMD_TERMINATOR, PCLK);
 114:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	plog("SSP1: frequency %u"CMD_TERMINATOR, frequency);
 115:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	plog("SSP1: div       %u"CMD_TERMINATOR, div);
 116:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	plog("SSP1: SSP1CPSR  %u"CMD_TERMINATOR, SSP1CPSR);
 117:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	#endif
 118:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 119:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	return (PCLK / div);
 120:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** }
  94              		.loc 1 120 0
  95 0020 B2FBF0F0 		udiv	r0, r2, r0
  96              	.LVL9:
  97 0024 7047     		bx	lr
  98              	.L9:
  99 0026 00BF     		.align	2
 100              	.L8:
 101 0028 40787D01 		.word	25000000
 102 002c 10000340 		.word	1073938448
 103              		.cfi_endproc
 104              	.LFE2:
 106              		.section	.text.spp1_SetMode,"ax",%progbits
 107              		.align	1
 108              		.global	spp1_SetMode
 109              		.thumb
 110              		.thumb_func
 112              	spp1_SetMode:
 113              	.LFB3:
 121:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 122:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //-------------------------------------------------------------------------------------------------
 123:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Descrição: 	Ajusta o modo de trabalho do barramento como mestre ou escravo
 124:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // parametros	mode: Modo da CPU
 125:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //					SSP1_MASTER
 126:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //					SSP1_SLAVE
 127:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Retorna: 	Retorna pdPASS se a seleção foi feito com sucesso senão retorna código do erro
 128:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //-------------------------------------------------------------------------------------------------
 129:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** int spp1_SetMode ( u8 mode ) {
 114              		.loc 1 129 0
 115              		.cfi_startproc
 116              		@ args = 0, pretend = 0, frame = 0
 117              		@ frame_needed = 0, uses_anonymous_args = 0
 118              		@ link register save eliminated.
 119              	.LVL10:
 130:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     n8 status;
 131:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 132:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     status = pdPASS;
 133:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 134:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     switch( mode ) {
 120              		.loc 1 134 0
 121 0000 08B1     		cbz	r0, .L13
 122 0002 0428     		cmp	r0, #4
 123 0004 04D1     		bne	.L16
 124              	.L13:
 135:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	case SSP1_MASTER:
 136:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****         	SSP1CR1 |= SSP1_MASTER; 				// Mestre
 137:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****         	break;
 138:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 139:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	case SSP1_SLAVE:
 140:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     		SSP1CR1 &= ~SSP1_MASTER; 			// escravo
 125              		.loc 1 140 0
 126 0006 034B     		ldr	r3, .L17
 132:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 127              		.loc 1 132 0
 128 0008 0120     		movs	r0, #1
 129              	.LVL11:
 130              		.loc 1 140 0
 131 000a 1A68     		ldr	r2, [r3]
 132 000c 1A60     		str	r2, [r3]
 141:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****         	break;
 133              		.loc 1 141 0
 134 000e 7047     		bx	lr
 135              	.LVL12:
 136              	.L16:
 142:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 143:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	default:
 144:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****         	status = errSPP1_ERROR_SET_MODE;
 137              		.loc 1 144 0
 138 0010 E120     		movs	r0, #225
 139              	.LVL13:
 145:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****         	break;
 146:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     }
 147:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 148:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     return status;
 149:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** }
 140              		.loc 1 149 0
 141 0012 7047     		bx	lr
 142              	.L18:
 143              		.align	2
 144              	.L17:
 145 0014 04000340 		.word	1073938436
 146              		.cfi_endproc
 147              	.LFE3:
 149              		.section	.text.ssp1_Init,"ax",%progbits
 150              		.align	1
 151              		.global	ssp1_Init
 152              		.thumb
 153              		.thumb_func
 155              	ssp1_Init:
 156              	.LFB0:
  32:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	u32 i;
 157              		.loc 1 32 0
 158              		.cfi_startproc
 159              		@ args = 0, pretend = 0, frame = 8
 160              		@ frame_needed = 0, uses_anonymous_args = 0
 161              	.LVL14:
 162 0000 07B5     		push	{r0, r1, r2, lr}
 163              	.LCFI0:
 164              		.cfi_def_cfa_offset 16
 165              		.cfi_offset 14, -4
  36:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	#if defined (arm7tdmi)
 166              		.loc 1 36 0
 167 0002 114A     		ldr	r2, .L22
 168 0004 1368     		ldr	r3, [r2]
 169 0006 43F48063 		orr	r3, r3, #1024
 170 000a 1360     		str	r3, [r2]
  55:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	#endif
 171              		.loc 1 55 0
 172 000c 0F4A     		ldr	r2, .L22+4
 173 000e 1368     		ldr	r3, [r2]
 174 0010 43F42823 		orr	r3, r3, #688128
 175 0014 1360     		str	r3, [r2]
  59:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	spp1_SetMode( mode );
 176              		.loc 1 59 0
 177 0016 0E4B     		ldr	r3, .L22+8
 178 0018 1960     		str	r1, [r3]
  60:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	SSP1IMSC = 0x0;
 179              		.loc 1 60 0
 180 001a FFF7FEFF 		bl	spp1_SetMode
 181              	.LVL15:
  61:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	
 182              		.loc 1 61 0
 183 001e 0D4B     		ldr	r3, .L22+12
 184 0020 0022     		movs	r2, #0
 185 0022 1A60     		str	r2, [r3]
  64:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 186              		.loc 1 64 0
 187 0024 0C48     		ldr	r0, .L22+16
 188 0026 FFF7FEFF 		bl	ssp1_SetClockFreq
 189              	.LVL16:
  67:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 190              		.loc 1 67 0
 191 002a 0C4A     		ldr	r2, .L22+20
  76:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** }
 192              		.loc 1 76 0
 193 002c 0C49     		ldr	r1, .L22+24
  67:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 194              		.loc 1 67 0
 195 002e 1368     		ldr	r3, [r2]
 196 0030 43F00203 		orr	r3, r3, #2
 197 0034 1360     		str	r3, [r2]
 198              	.LVL17:
 199 0036 0823     		movs	r3, #8
 200              	.LVL18:
 201              	.L20:
  76:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** }
 202              		.loc 1 76 0 discriminator 3
 203 0038 0A68     		ldr	r2, [r1]
  75:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	dummy = SSP1DR;
 204              		.loc 1 75 0 discriminator 3
 205 003a 013B     		subs	r3, r3, #1
 206              	.LVL19:
  76:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** }
 207              		.loc 1 76 0 discriminator 3
 208 003c 0192     		str	r2, [sp, #4]
 209              	.LVL20:
  75:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	dummy = SSP1DR;
 210              		.loc 1 75 0 discriminator 3
 211 003e FBD1     		bne	.L20
  77:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 212              		.loc 1 77 0
 213 0040 03B0     		add	sp, sp, #12
 214              	.LCFI1:
 215              		.cfi_def_cfa_offset 4
 216              		@ sp needed
 217 0042 5DF804FB 		ldr	pc, [sp], #4
 218              	.L23:
 219 0046 00BF     		.align	2
 220              	.L22:
 221 0048 C4C00F40 		.word	1074774212
 222 004c 00C00240 		.word	1073922048
 223 0050 00000340 		.word	1073938432
 224 0054 14000340 		.word	1073938452
 225 0058 801A0600 		.word	400000
 226 005c 04000340 		.word	1073938436
 227 0060 08000340 		.word	1073938440
 228              		.cfi_endproc
 229              	.LFE0:
 231              		.section	.text.ssp1_WaitReady,"ax",%progbits
 232              		.align	1
 233              		.global	ssp1_WaitReady
 234              		.thumb
 235              		.thumb_func
 237              	ssp1_WaitReady:
 238              	.LFB4:
 150:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 151:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //-------------------------------------------------------------------------------------------------
 152:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Descrição: 	Espera pelo cartão ficar pronto
 153:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Parametros:	Nenhum
 154:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Retorna:		Retorna sempre 0xFF
 155:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //-------------------------------------------------------------------------------------------------
 156:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** u8 ssp1_WaitReady(void) {
 239              		.loc 1 156 0
 240              		.cfi_startproc
 241              		@ args = 0, pretend = 0, frame = 0
 242              		@ frame_needed = 0, uses_anonymous_args = 0
 157:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	u8 res;
 158:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 159:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	do {      
 160:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	SSP1DR = 0xff;
 243              		.loc 1 160 0
 244 0000 064B     		ldr	r3, .L30
 156:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	u8 res;
 245              		.loc 1 156 0
 246 0002 10B5     		push	{r4, lr}
 247              	.LCFI2:
 248              		.cfi_def_cfa_offset 8
 249              		.cfi_offset 4, -8
 250              		.cfi_offset 14, -4
 251 0004 1A46     		mov	r2, r3
 161:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	while (!(SSP1SR & SSP1_RNE));
 252              		.loc 1 161 0
 253 0006 064C     		ldr	r4, .L30+4
 160:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	while (!(SSP1SR & SSP1_RNE));
 254              		.loc 1 160 0
 255 0008 FF21     		movs	r1, #255
 256              	.L26:
 257 000a 1960     		str	r1, [r3]
 258              	.L25:
 259              		.loc 1 161 0 discriminator 1
 260 000c 2068     		ldr	r0, [r4]
 261 000e 4007     		lsls	r0, r0, #29
 262 0010 FCD5     		bpl	.L25
 162:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	res = SSP1DR;
 263              		.loc 1 162 0
 264 0012 1068     		ldr	r0, [r2]
 265              	.LVL21:
 163:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	} while (res != 0xff);
 266              		.loc 1 163 0
 267 0014 C0B2     		uxtb	r0, r0
 268 0016 FF28     		cmp	r0, #255
 269 0018 F7D1     		bne	.L26
 164:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 165:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	return res;
 166:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** }
 270              		.loc 1 166 0
 271 001a 10BD     		pop	{r4, pc}
 272              	.L31:
 273              		.align	2
 274              	.L30:
 275 001c 08000340 		.word	1073938440
 276 0020 0C000340 		.word	1073938444
 277              		.cfi_endproc
 278              	.LFE4:
 280              		.section	.text.ssp1_TransferByte,"ax",%progbits
 281              		.align	1
 282              		.global	ssp1_TransferByte
 283              		.thumb
 284              		.thumb_func
 286              	ssp1_TransferByte:
 287              	.LFB5:
 167:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 168:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //-------------------------------------------------------------------------------------------------
 169:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Descrição: 	Troca de bytes entre os dispositivos
 170:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Parametros:	Byte a ser enviado
 171:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Retorna:		Byte Recebido
 172:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //-------------------------------------------------------------------------------------------------
 173:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** u8 ssp1_TransferByte (u8 c) {
 288              		.loc 1 173 0
 289              		.cfi_startproc
 290              		@ args = 0, pretend = 0, frame = 0
 291              		@ frame_needed = 0, uses_anonymous_args = 0
 292              		@ link register save eliminated.
 293              	.LVL22:
 174:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 	while (!(SSP1SR & SSP1_TNF)); // Espere se a FIFO estiver cheia
 294              		.loc 1 174 0
 295 0000 064A     		ldr	r2, .L38
 296              	.L33:
 297              		.loc 1 174 0 is_stmt 0 discriminator 1
 298 0002 1368     		ldr	r3, [r2]
 299 0004 0549     		ldr	r1, .L38
 300 0006 13F0020F 		tst	r3, #2
 301 000a FAD0     		beq	.L33
 175:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	SSP1DR = c;
 302              		.loc 1 175 0 is_stmt 1
 303 000c 044B     		ldr	r3, .L38+4
 304 000e 1860     		str	r0, [r3]
 305              	.L34:
 176:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	while (SSP1SR & SSP1_BSY);
 306              		.loc 1 176 0 discriminator 1
 307 0010 0A68     		ldr	r2, [r1]
 308 0012 D206     		lsls	r2, r2, #27
 309 0014 FCD4     		bmi	.L34
 177:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 178:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	return SSP1DR;
 310              		.loc 1 178 0
 311 0016 1868     		ldr	r0, [r3]
 312              	.LVL23:
 179:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** }
 313              		.loc 1 179 0
 314 0018 C0B2     		uxtb	r0, r0
 315 001a 7047     		bx	lr
 316              	.L39:
 317              		.align	2
 318              	.L38:
 319 001c 0C000340 		.word	1073938444
 320 0020 08000340 		.word	1073938440
 321              		.cfi_endproc
 322              	.LFE5:
 324              		.section	.text.ssp1_SendBlock,"ax",%progbits
 325              		.align	1
 326              		.global	ssp1_SendBlock
 327              		.thumb
 328              		.thumb_func
 330              	ssp1_SendBlock:
 331              	.LFB6:
 180:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 181:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //-------------------------------------------------------------------------------------------------
 182:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Descrição:	Envia um buffer de dados para o dispositivo ignorando o que recebe
 183:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Parametros: 	*pData: Ponteiro do buffer a ser transmitido
 184:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //				size: tamanho do buffer
 185:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Retorna:		Nada
 186:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //-------------------------------------------------------------------------------------------------
 187:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** void ssp1_SendBlock(const u8 *pData, u32 size) {
 332              		.loc 1 187 0
 333              		.cfi_startproc
 334              		@ args = 0, pretend = 0, frame = 8
 335              		@ frame_needed = 0, uses_anonymous_args = 0
 336              	.LVL24:
 188:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	volatile u32 dummy __attribute__ ((unused)); // Usar atributo para não emitir aviso pelo compila
 189:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 190:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	while (size--)  {
 191:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   		while (!(SSP1SR & SSP1_TNF)); // Espere se a FIFO estiver cheia
 337              		.loc 1 191 0
 338 0000 0A4B     		ldr	r3, .L50
 192:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	SSP1DR = *pData++;
 339              		.loc 1 192 0
 340 0002 0B4A     		ldr	r2, .L50+4
 187:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	volatile u32 dummy __attribute__ ((unused)); // Usar atributo para não emitir aviso pelo compila
 341              		.loc 1 187 0
 342 0004 73B5     		push	{r0, r1, r4, r5, r6, lr}
 343              	.LCFI3:
 344              		.cfi_def_cfa_offset 24
 345              		.cfi_offset 4, -16
 346              		.cfi_offset 5, -12
 347              		.cfi_offset 6, -8
 348              		.cfi_offset 14, -4
 349 0006 1C46     		mov	r4, r3
 350 0008 1546     		mov	r5, r2
 351 000a 0144     		add	r1, r1, r0
 352              	.LVL25:
 353              	.L41:
 190:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   		while (!(SSP1SR & SSP1_TNF)); // Espere se a FIFO estiver cheia
 354              		.loc 1 190 0
 355 000c 8842     		cmp	r0, r1
 356 000e 0BD0     		beq	.L49
 357              	.L46:
 191:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	SSP1DR = *pData++;
 358              		.loc 1 191 0 discriminator 1
 359 0010 1E68     		ldr	r6, [r3]
 360 0012 B607     		lsls	r6, r6, #30
 361 0014 FCD5     		bpl	.L46
 362              		.loc 1 192 0
 363 0016 10F8016B 		ldrb	r6, [r0], #1	@ zero_extendqisi2
 364              	.LVL26:
 365 001a 1660     		str	r6, [r2]
 366              	.L43:
 193:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	while (!(SSP1SR & SSP1_RNE));
 367              		.loc 1 193 0 discriminator 1
 368 001c 2668     		ldr	r6, [r4]
 369 001e 7607     		lsls	r6, r6, #29
 370 0020 FCD5     		bpl	.L43
 194:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	dummy = SSP1DR;
 371              		.loc 1 194 0
 372 0022 2E68     		ldr	r6, [r5]
 373 0024 0196     		str	r6, [sp, #4]
 374 0026 F1E7     		b	.L41
 375              	.LVL27:
 376              	.L49:
 195:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	}
 196:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** }
 377              		.loc 1 196 0
 378 0028 02B0     		add	sp, sp, #8
 379              	.LCFI4:
 380              		.cfi_def_cfa_offset 16
 381              		@ sp needed
 382 002a 70BD     		pop	{r4, r5, r6, pc}
 383              	.L51:
 384              		.align	2
 385              	.L50:
 386 002c 0C000340 		.word	1073938444
 387 0030 08000340 		.word	1073938440
 388              		.cfi_endproc
 389              	.LFE6:
 391              		.section	.text.ssp1_ReceiveBlock,"ax",%progbits
 392              		.align	1
 393              		.global	ssp1_ReceiveBlock
 394              		.thumb
 395              		.thumb_func
 397              	ssp1_ReceiveBlock:
 398              	.LFB7:
 197:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 198:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //-------------------------------------------------------------------------------------------------
 199:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Descrição:	Recebe um buffer de dados do dispositivo, onde este ignora os dados enviados
 200:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Parametros: 	*pData: Ponteiro do buffer a ser preenchido com os dados recebidos
 201:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //				size: tamanho do buffer
 202:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** // Retorna:		Nada
 203:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** //-------------------------------------------------------------------------------------------------
 204:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** void ssp1_ReceiveBlock(u8 *pData, u32 size) {
 399              		.loc 1 204 0
 400              		.cfi_startproc
 401              		@ args = 0, pretend = 0, frame = 0
 402              		@ frame_needed = 0, uses_anonymous_args = 0
 403              	.LVL28:
 404 0000 F0B5     		push	{r4, r5, r6, r7, lr}
 405              	.LCFI5:
 406              		.cfi_def_cfa_offset 20
 407              		.cfi_offset 4, -20
 408              		.cfi_offset 5, -16
 409              		.cfi_offset 6, -12
 410              		.cfi_offset 7, -8
 411              		.cfi_offset 14, -4
 205:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	u32 delta = 0;
 206:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 207:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	while (size || delta) {
 208:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	while ((SSP1SR & SSP1_TNF) && (delta < SSP1_FIFO_DEPTH) && size) {
 412              		.loc 1 208 0
 413 0002 114D     		ldr	r5, .L63
 209:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****       		SSP1DR = 0xff;
 414              		.loc 1 209 0
 415 0004 114E     		ldr	r6, .L63+4
 416 0006 AE46     		mov	lr, r5
 205:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	u32 delta = 0;
 417              		.loc 1 205 0
 418 0008 0023     		movs	r3, #0
 419              		.loc 1 209 0
 420 000a FF27     		movs	r7, #255
 421              	.LVL29:
 422              	.L53:
 207:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	while ((SSP1SR & SSP1_TNF) && (delta < SSP1_FIFO_DEPTH) && size) {
 423              		.loc 1 207 0
 424 000c 01B9     		cbnz	r1, .L59
 207:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	while ((SSP1SR & SSP1_TNF) && (delta < SSP1_FIFO_DEPTH) && size) {
 425              		.loc 1 207 0 is_stmt 0 discriminator 1
 426 000e D3B1     		cbz	r3, .L52
 427              	.L59:
 204:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	u32 delta = 0;
 428              		.loc 1 204 0 is_stmt 1
 429 0010 1A46     		mov	r2, r3
 430              	.LVL30:
 431              	.L61:
 208:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****       		SSP1DR = 0xff;
 432              		.loc 1 208 0
 433 0012 2B68     		ldr	r3, [r5]
 434 0014 9B07     		lsls	r3, r3, #30
 435 0016 01D4     		bmi	.L54
 436              	.L56:
 204:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****   	u32 delta = 0;
 437              		.loc 1 204 0
 438 0018 0446     		mov	r4, r0
 439 001a 07E0     		b	.L55
 440              	.L54:
 208:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****       		SSP1DR = 0xff;
 441              		.loc 1 208 0 discriminator 1
 442 001c 072A     		cmp	r2, #7
 443 001e FBD8     		bhi	.L56
 208:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****       		SSP1DR = 0xff;
 444              		.loc 1 208 0 is_stmt 0 discriminator 2
 445 0020 0029     		cmp	r1, #0
 446 0022 F9D0     		beq	.L56
 447              		.loc 1 209 0 is_stmt 1
 448 0024 3760     		str	r7, [r6]
 210:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****       		--size; 
 449              		.loc 1 210 0
 450 0026 0139     		subs	r1, r1, #1
 451              	.LVL31:
 211:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****       		++delta;
 452              		.loc 1 211 0
 453 0028 0132     		adds	r2, r2, #1
 454              	.LVL32:
 455 002a F2E7     		b	.L61
 456              	.LVL33:
 457              	.L55:
 212:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	}
 213:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c **** 
 214:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****     	while (SSP1SR & SSP1_RNE) {
 458              		.loc 1 214 0
 459 002c DEF800C0 		ldr	ip, [lr]
 460 0030 131B     		subs	r3, r2, r4
 461 0032 1CF0040F 		tst	ip, #4
 462 0036 0344     		add	r3, r3, r0
 463              	.LVL34:
 464 0038 03D0     		beq	.L62
 215:uc_libc_dev/_arch/arm_lpc/spi/ssp1.c ****       		*pData++ = SSP1DR;
 465              		.loc 1 215 0
 466 003a 3368     		ldr	r3, [r6]
 467              	.LVL35:
 468 003c 04F8013B 		strb	r3, [r4], #1
 469              	.LVL36:
 470 0040 F4E7     		b	.L55
 471              	.LVL37:
 472              	.L62:
 473 0042 2046     		mov	r0, r4
 474 0044 E2E7     		b	.L53
 475              	.LVL38:
 476              	.L52:
 477 0046 F0BD     		pop	{r4, r5, r6, r7, pc}
 478              	.L64:
 479              		.align	2
 480              	.L63:
 481 0048 0C000340 		.word	1073938444
 482 004c 08000340 		.word	1073938440
 483              		.cfi_endproc
 484              	.LFE7:
 486              		.text
 487              	.Letext0:
 488              		.file 2 "uc_libc_dev/_libdef/uc_libdefs.h"
DEFINED SYMBOLS
                            *ABS*:00000000 ssp1.c
D:\_temp\_windows\ccf84Egd.s:20     .text.spi1_SetBitsPerTransfer:00000000 $t
D:\_temp\_windows\ccf84Egd.s:25     .text.spi1_SetBitsPerTransfer:00000000 spi1_SetBitsPerTransfer
D:\_temp\_windows\ccf84Egd.s:48     .text.spi1_SetBitsPerTransfer:00000014 $d
D:\_temp\_windows\ccf84Egd.s:53     .text.ssp1_SetClockFreq:00000000 $t
D:\_temp\_windows\ccf84Egd.s:58     .text.ssp1_SetClockFreq:00000000 ssp1_SetClockFreq
D:\_temp\_windows\ccf84Egd.s:101    .text.ssp1_SetClockFreq:00000028 $d
D:\_temp\_windows\ccf84Egd.s:107    .text.spp1_SetMode:00000000 $t
D:\_temp\_windows\ccf84Egd.s:112    .text.spp1_SetMode:00000000 spp1_SetMode
D:\_temp\_windows\ccf84Egd.s:145    .text.spp1_SetMode:00000014 $d
D:\_temp\_windows\ccf84Egd.s:150    .text.ssp1_Init:00000000 $t
D:\_temp\_windows\ccf84Egd.s:155    .text.ssp1_Init:00000000 ssp1_Init
D:\_temp\_windows\ccf84Egd.s:221    .text.ssp1_Init:00000048 $d
D:\_temp\_windows\ccf84Egd.s:232    .text.ssp1_WaitReady:00000000 $t
D:\_temp\_windows\ccf84Egd.s:237    .text.ssp1_WaitReady:00000000 ssp1_WaitReady
D:\_temp\_windows\ccf84Egd.s:275    .text.ssp1_WaitReady:0000001c $d
D:\_temp\_windows\ccf84Egd.s:281    .text.ssp1_TransferByte:00000000 $t
D:\_temp\_windows\ccf84Egd.s:286    .text.ssp1_TransferByte:00000000 ssp1_TransferByte
D:\_temp\_windows\ccf84Egd.s:319    .text.ssp1_TransferByte:0000001c $d
D:\_temp\_windows\ccf84Egd.s:325    .text.ssp1_SendBlock:00000000 $t
D:\_temp\_windows\ccf84Egd.s:330    .text.ssp1_SendBlock:00000000 ssp1_SendBlock
D:\_temp\_windows\ccf84Egd.s:386    .text.ssp1_SendBlock:0000002c $d
D:\_temp\_windows\ccf84Egd.s:392    .text.ssp1_ReceiveBlock:00000000 $t
D:\_temp\_windows\ccf84Egd.s:397    .text.ssp1_ReceiveBlock:00000000 ssp1_ReceiveBlock
D:\_temp\_windows\ccf84Egd.s:481    .text.ssp1_ReceiveBlock:00000048 $d
                     .debug_frame:00000010 $d

NO UNDEFINED SYMBOLS
